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Nowadays, a printed circuit board of any modern electronic device should meet the requirements of technologically advanced solutions. That is why high speed and high-frequency PCB design has become a hot topic for hardware engineering professionals.
All high-tech devices are designed with a high speed PCB thanks to which the size of the devices is getting smaller, data transfer is getting faster and the devices themselves are becoming more functional and handy.
That is why it is really important for every PCB designer to know high speed board design basics. If you are in the loop already, go ahead, take a shot and design a high speed PCB. Doing this, you will get the necessary skills and experience, uplevel yourself, and stay a go-to engineer.Our team has already had such experience performing on high speed PCB design projects. So we decided to write this article to underscore the relevance of its topic and share our personal experience.We hope our high speed design guidelines supported by first-hand recommendations will be helpful to designers who make their first steps in exploring this area.DDR3 interface layout
This picture illustrates a part of high speed PCB design developed by our engineers for a home automation system. Our team managed to meet all the challenges and achieved great results in the development of.
Aligning rules for differential pairs layout (Altium Designer)
Tuned length of tracks
Tuned differential pair
Tuned parallel interface
Impedance
When you make a PCB layout or a high speed PCB layout, you should observe single-ended impedance Zo as well as differential impedance Zdiff.As a refresher: single-ended impedance is the impedance of single tracks that are not united into differential pairs. Differential impedance is the impedance between a pair of coupled tracks.There are typical impedance values for each interface both parallel and serial. There are also other types of impedance:Parameters for Zdiff calculation
Track shape
You can hardly ever meet straight tracks from the sources to the receiver on boards. Especially in the context of high speed interfaces where you have to bend the tracks while tuning their lengths.Ideally, tracks should have rounded, smooth corners without sharp bends. However, you need plenty of time to achieve this.What makes such a design even more time-consuming is that you redraw each track several times during the layout optimization.The worst case is to bend tracks at 90-degree angles. The thing is that the width of the track changes drastically at the bends. As a result, impedance changes in these places and reflections appear in the track. In the case of differential pairs, this also leads to a higher value of uncoupled length.For this reason, the best option is to bend tracks at an angle of 45 degrees.Tracks bent at 45 degrees
Termination
Today the most common type of termination is parallel termination. The idea is to place a resistor between the tracks of a differential pair at the end of the line, as close to the receiver as possible.Termination makes it possible to effectively get rid of signal reflections in the tracks, therefore, upgrading the quality of data transfer. In the case of differential pairs, resistor value should be equal or a little more than Zdiff.The low value of the resistor will cause over-termination which will adversely impact the signal quality.Some ICs have termination resistors inside. In this case, you do not need external resistors because they will cause over-termination. That’s why it is important to learn datasheets and hardware design guides for all ICs you use.Termination resistor for a differential pair
Grounding
In most cases, you cannot trace high speed interfaces on one layer. Thus you need to move traces to the other layers with the help of vias. Vias are electroplated holes through which traces can connect with each other on different board layers. GND polygons potential on different layers should be the same near signal vias. That's why you should place GND vias as close to them as possible. Such GND vias are called stitching vias. This approach allows keeping the same GND reference all along the high speed trace.However, you should be careful with using vias for high speed signal routing. Thus, densely populated vias can lead to high current density and consequently overheating. When placing vias, make sure there is enough space between them. The improper design of vias can cause impedance discontinuities. To avoid this, all vias should have an appropriate diameter either on the board layout or on the manufactured PCB.Stitching vias near the signal vias
Components location
Components’ placement is an important point in the high speed PCB layout rules. Before you begin, try to map out the location of the components on your board. For example, you can sort out the components according to their functionality. If they take part in one and the same process or perform similar functions, you should locate them close to each other. Analog components (if there are any on the board) should have their own GND polygon. In addition, you should place them separately from digital components and traces to avoid EMI. Before placing the high speed components, remember that the traces are not very long. So make sure you leave enough space for the length tuning. There is no point in placing such components very close to the interference sources, such as switching power converters. Moreover, you shouldn`t place components relating to high speed interfaces too close to the edge of the board. Such placement has a negative impact on signal quality. It’s better to move such components to the center of the board, leaving the connectors on the edge. The components’ location becomes a real challenge when a PCB is of a very small size. Following the location rules for high speed design, we placed the components in the most accurate manner on a small PCB forMutual location of CPU and DDR3 memory chip. ICs are connected to each other through a high speed interface. There is enough space for the length tuning and ICs are still not placed too far from each other (interface tracks are not too long).
Placement of ground polygons on the layers close to the signal layers
You should route tracks of high speed interfaces over a solid GND plane. We do not recommend you route tracks over cutouts in polygons or over polygon-splits. Otherwise, you will get extra EMI, signal propagation delays, integrity violation, generation of interference and finally, degradation of the signal quality.If the tracks happen to cross polygon-splits, it is necessary to place ceramic stitching capacitors at the place of polygons splitting. This will minimize the negative impact on the signal.DDR3 interface routing above a solid GND polygon
Crosstalk
Crosstalk is a phenomenon that takes place when a signal transmitted over one communication track raises an unwanted effect in the other tracks. The effect shows as a change in signal and in most cases, the tracks are neighboring.Crosstalk depends on the length of the section where the tracks run parallel with each other. The longer the section’s length, the higher the crosstalk.To minimize crosstalk, it is necessary to make the distance between the tracks at least three times longer than the track’s width (3W rule).To minimize crosstalk between differential pairs, the distance between the differential pairs should be at least five times longer than the track’s width (5W rule). Keep the same distance between differential pairs and any other tracks along the full length of the differential pair.If a differential pair serves to transmit a periodic signal, e.g. clocking, we recommend you increase the distance from this differential pair to the other differential pairs or any other tracks up to 8-10W.Pay special attention to the tracks of asynchronous signals (enable, interrupt, reset, etc.). You should make the distance between these tracks and tracks with high speed signals as long as possible.Sometimes we use two neighboring layers in a multilayer printed circuit board to route signals. Doing this, remember to route the tracks on one layer perpendicular to the tracks on the second layer. Thus you will avoid parallelism of the tracks and minimize crosstalk between them.3W distance between parallel tracks
We have mentioned the basic high speed PCB board design rules but not all of them. This is a wide area of an even much wider area called PCB design.In its turn, PCB design is a part of such a vast and multistage domain as embedded hardware development. It includes, for instance, preparation for production and selection of components. At these stages, you should consider bazillion nuances such as the device production time and the scheduled time for discontinued components, etc.We can take care of all the details delivering your project as part of embedded hardware design and development services that we provide.The picture shows one and the same impedance depending on the distance to the GND layer. The longer the distance, the thicker the track.
Don’t forget to ask your manufacturer to perform the impedance control procedure. Such a procedure will add to the cost of manufacturing but will allow the designer to increase the quality of high speed signals on the PCB.It is always very useful to get new knowledge and adopt experience from other developers for both newcomers and advanced engineers. Our engineers are no exception. They are constantly trying to replenish their store of knowledge and move with the times.One of the most efficient methods of doing that is to take various courses and training programs. From our personal experience, we would recommend Advanced PCB Layout Course by . They provide high speed PCB layout guidelines that will help you improve yourself.Fedevel Academy Certificate awarded to Integra’s PCB designer.
For newcomers, this course can help teach how to start, what to do first, what to do next, how to check every part of the PCB, how to create output documentation, and a lot of other information. Experienced engineers will be able to learn a lot of useful PCB design tips and tricks which can save plenty of time.Layout error detected by the Design Rule Check
The screenshot above shows how the rule in the DRC works. We set an acceptable propagation value and after the rules are checked, a mismatched track is detected.Another new feature proposed in Altium Designer 20 is Interactive Sliding. This function tackles a number of issues that you might face during high speed layout. The picture below shows a preferred way to lay out a BGA microcontroller.BGA MCU layout with Interactive Sliding
Interactive Sliding assists greatly in the design of non-standard printed circuit boards, such as ring-shaped PCBs.Moon-shaped PCB design
Altium has a wide range of interesting features including their collaboration with GitLab and SolidWorks. You can look through all GitLab threads, track the detailed change history, and push changes directly from Altium. SolidWorks Collaboration makes it possible to edit a board straight in SolidWorks. You open a 3D model, place the components, save changes, and then just edit the tracks in Altium.
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